Why does the compile time increase when using the "[get_registers *]" collection in my Synopsys Design Constraints (SDC) file? - Why does the compile time increase when using the "[get_registers *]" collection in my Synopsys Design Constraints (SDC) file? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and earlier, you might see a compile time increase when using the "[get_registers *]" collection in your Synopsys Design Constraints (SDC) files. Resolution To work around this problem, replace the "[get_registers *]" collection with a single wildcard "*". This problem was fixed in version 22.1 of Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18018855561 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 21.3 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']