Demonstration Testbench for Some CPRI IP Core Verilog HDL Variations Fails Simulation of HDLC Functionality - Demonstration Testbench for Some CPRI IP Core Verilog HDL Variations Fails Simulation of HDLC Functionality Description If you generate a Verilog HDL model for a CPRI IP core variation that has a data rate of 4.915 Gbps, 6.144 Gbps, or 9.8 Gbps and targets an Arria V GZ, Arria V GT, or Stratix V device, the Verilog HDL model fails simulation of HDLC functionality with the demonstration testbench. The IP core drops some HDLC data. Resolution This issue has no workaround. Generate and simulate a VHDL model instead of a Verilog HDL model for these CPRI IP core variations, if you want to simulate HDLC functionality. This issue will be fixed in a future version of the CPRI MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Interfaces Communications CPRI (Primary)'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']