Instantiation of x-1 LOW LATENCY PHYmegafunction with 10GB PCS and more than six channels fails for Stratix V - Instantiation of x-1 LOW LATENCY PHYmegafunction with 10GB PCS and more than six channels fails for Stratix V Description If you attempt to instantiate a x-1 LOW LATENCY PHYmegafunction that uses 10GB PCS and more than six channels, fitting fails because the PLL cannot drive more than six channels. The Fitter generates messages similar to the following: Error: Could not place ATX PLL hsl2_rev1:inst24|altera_xcvr_low_latency_phy:h sl2_rev1_inst|alt_pma:alt_pma_inst|alt_pma_sv: alt_pma_sv_inst|altera_xcvr_10g_custom:altera_ xcvr_10g_custom_inst|pll[0].tx_pll~LC_PLL. Resolution Instantiate a x-1 design for one channel, and then repeat the instantiation to meet the number of channels you require. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']