Why do I see elaboration errors on the Cadence Xcelium* simulator when using the Agilex™ 7 F-Tile IPs? - Why do I see elaboration errors on the Cadence Xcelium* simulator when using the Agilex™ 7 F-Tile IPs? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, Agilex™ 7 F-Tile IPs may show elaboration time errors when using the Cadence Xcelium* simulator similar to the error shown below: xmelab: *E,CUVIMG (<QUARTUS_INSTALL_DIR>/ libraries/megafunctions/ftileb_ag_v0.sv,624316): Implicit name not allowed in hierarchical name. Resolution To workaround this problem, use the following Cadence Xcelium* simulator-specific option: xmelab: *E,CUVIMG (<QUARTUS_INSTALL_DIR>/libraries/megafunctions/ftileb_ag_v0.sv,624316): Implicit name not allowed in hierarchical name. Use elaboration switch ( -genhier ) in the simulation compilation script. Example: xmelab -genhier -relax -timescale '1 ps / 1 fs' -genhier -access +rwc <top_level_name> This problem has been fixed in version 24.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14021047956, 14020944878 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']