Why does rx_st_valid deassert between packets on the Avalon-ST bus in simulation? - Why does rx_st_valid deassert between packets on the Avalon-ST bus in simulation? Description In simulation, the testbench or bus functional model (BFM) might be unable to send continuous PCI Express® (PCIe) transactions. This inability results in rx_st_valid deasserting between some or all packets on the Avalon®-ST bus. Resolution The Altera® Hard IP for PCI Express® is capable of continuous Avalon-ST packets, but to observe this the testbench or BFM must be capable of sending continuous PCIe transactions. Refer to the attached screenshot for an example of a BFM which sends continuous PCIe transactions. You must modify your testbench or BFM to supply continuous PCIe transactions to keep rx_st_valid asserted between Avalon-ST packets. For example throughput measurements, please refer to the following application note pages: http://www.altera.com/literature/an/an456.pdf#page=20 http://www.altera.com/literature/an/an690.pdf#page=19 Custom Fields values: ['novalue'] Troubleshooting n/a False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']