How many outstanding read request can Stratix V Hard IP for PCI Express with Avalon-MM interface (bridge) handle ? - How many outstanding read request can Stratix V Hard IP for PCI Express with Avalon-MM interface (bridge) handle ? Description Stratix ® V Hard IP for PCI Express ® with Avalon-MM interface (bridge) supports up to 8 outstanding reads from Avalon-MM interface. After 8 reads are accepted by the bridge and before any completion data has returned, the TxsWaitRequest signal will be asserted to block additional reads. Additional reads can be accepted by the bridge only after previous reads has been completed. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']