DisplayPort Sink | 2 Pixel per Clock Video | Output not correct - DisplayPort Sink | 2 Pixel per Clock Video | Output not correct Hi, I am using a DisplayPort IP core as sink, two 2.7 GB lanes, 1920 x 1080. It works perfectly with 1 pixel per clock. For a new project I need video data with even and odd pixels output So I configured the IP core with 2 pixel per clock and after generation the video data output port of the clock recovery core has a width of 48 bit as expected. But only the lower 24 bits contain video data, the upper 24 bits are always 0. The pixel clock output of the clock recovery core amounts to 74.5 MHz, the clockx2 output 149 MHz. So the clocks seem to be correct. Is there some additional setting i have to configure to get a 2 pixel per clock 48 bit video output? Replies: Re: DisplayPort Sink | 2 Pixel per Clock Video | Output not correct HI, Np, I am glad that you fix the issue Alright, I am now setting this case to closure. Regards, dlim Replies: Re: DisplayPort Sink | 2 Pixel per Clock Video | Output not correct Hi! Thank you for yor reply! Finally, I found the cause of the issue with video data output in my DisplayPort top level module. A vector had the wrong size. Regards Wolfram Replies: Re: DisplayPort Sink | 2 Pixel per Clock Video | Output not correct HI, You can learn more about expected video data interface output from DP user guide doc (chapter 6.5.4, page 102) https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf You may also want to monitor rxN_vid_valid signal assertion to detect the active video Like wise you can also try generate DIsplayPort example design and monitor the vide traffic transaction. Thanks. Regards, dlim