Why does the JESD204C Intel® FPGA IP TX output port j204c_tx_avst_ready remain low when configured in Subclass 1 mode with CSR optimization parameter enabled? - Why does the JESD204C Intel® FPGA IP TX output port j204c_tx_avst_ready remain low when configured in Subclass 1 mode with CSR optimization parameter enabled? Description Due to a known problem in Intel® Quartus® Prime Pro Edition Software version 21.1 and earlier, when the JESD204C Intel® FPGA IP is used in TX mode in Intel® Stratix® 10 FPGA or Intel Agilex® 7 devices and is configured to Subclass 1 mode with CSR Optimization enabled, the Avalon-ST signal j204c_tx_avst_ready stays low forever. This problem does not affect either Subclass 0 variants with CSR Optimization enabled or Subclass 1 variants with CSR Optimization disabled. Resolution There is no workaround for this problem. To avoid this issue, do not use the CSR Optimization feature in Subclass 1 mode. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2. Custom Fields values: ['novalue'] Troubleshooting 1508825040 1508919889 False ['JESD'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 19.2 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']