Why does synthesis hang when inferring a mixed-width RAM? - Why does synthesis hang when inferring a mixed-width RAM? Description Due to problem in Quartus® Prime Pro Edition Software version 17.0 or earlier, synthesis stage would hang when infering a mixed width RAM with a 1-bit wide port in a design. Resolution To work around this problem, instantiate the RAM from the IP catalog with same parameter settings instead of using RTL coding to infer the RAM. This problem is fixed starting with the Quartus® Prime Pro Edition Software version 17.1. Custom Fields values: ['novalue'] Troubleshooting FB: 474255; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 17.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']