Why does quartus_hps fail to reprogram my QSPI device? - Why does quartus_hps fail to reprogram my QSPI device? Description The quartus_hps programmer may fail during programming of an HPS attached quad serial peripheral interface (SPI/QSPI) devices on Cyclone® V SoC, Arria® V SoC, or Intel® Arria® 10 FPGA systems if the QSPI contains an existing, or corrupted image. The following error messages may be seen: Error: Fail to match data at flash address <address> with file address <address>. Error: Fail to read Silicon ID Quad SPI Flash silicon ID is 0x00000000 Resolution In the Intel Quartus® Prime Software version 16.1 and later, the --boot=18 option can be used with quartus_hps to resolve this problem. The --boot=18 option causes a cold reset to be applied to the SoC before quad SPI programming, which resets all clocks to default values. For example: quartus_hps -c 1 -o PV --boot=18 -a 0x0 <filename>.img This option is scheduled to be documented in a future version of the SoC EDS Handbook. Additionally: Suppose instability is seen during programming using an Intel® FPGA Download Cable II (formerly known as the USB Blaster II cable)—on-board or separate cable. In that case, it may help to slow down the JTAG interface speed: How do I change the clock frequency of the USB-Blaster II download cable? A patch including the --boot=18 option is available for the Intel Quartus Prime Software version 16.0, see: Error: Fail to read Silicon ID This problem is fixed starting with the Intel® Quartus® Prime Software 17.0 version. Custom Fields values: ['novalue'] Troubleshooting FB: 336330 452910; True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 16.1 ['Arria® V SX FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Cyclone® Bare Die'] ['Embedded Dev Tools SoC Suite'] ['novalue'] ['novalue']