LL 40-100GbE IP Core Hardware Design Example Requires New SDC File - LL 40-100GbE IP Core Hardware Design Example Requires New SDC File Description The LL 40-100GbE IP core hardware design example fails timing. The issue is caused by clock name mismatches with the SDC file. Resolution To ensure the hardware design example can run correctly, you must replace the contents of the SDC file at <example_design_install_dir>/hardware_test_design/common/common_timing_a10.sdc with the following text: derive_pll_clocks -create_base_clock derive_clock_uncertainty set_false_path -from [get_keepers {cpu_resetn}] set RX_CORE_CLK [get_clocks *|phy*|*rxp|*rx_pll*rx_core_clk*] set TX_CORE_CLK [get_clocks *|phy*|*txp|*tx_pll*tx_core_clk] set clk100 [get_clocks *|iopll*|clk100] set_clock_groups -asynchronous -group -group -group This issue will be fixed in a future version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']