What are the active bit mappings of the Native PHY rx_parallel_data and tx_parallel_data busses when the "Enable simplified data interface" is disabled for Stratix V, Arria V, and Cyclone V transceiver devices? - What are the active bit mappings of the Native PHY rx_parallel_data and tx_parallel_data busses when the "Enable simplified data interface" is disabled for Stratix V, Arria V, and Cyclone V transceiver devices? Description The active bit mappings of the Native PHY rx_parallel_data and tx_parallel_data busses when the "Enable simplified data interface" is disabled for Stratix® V, Arria® V, and Cyclone® V transceiver devices is listed in the transceiver Native PHY Megawizard™ message pane. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']