Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example - Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example Dear Experts, I am reaching out to seek assistance with a compilation error I am encountering while working on a project with Intel Quartus Prime 23.3. I have downloaded the project files(qar) from the following link: https://www.rocketboards.org/foswiki/pub/Documentation/AgilexPcieRootPort/ROOTPORT_Release_1_0_ptile_4x4_hps.qar The error message I am facing during the compilation process is as follows: Error ID: 22501 ptile_4x4/dni/sandboxes/35236_0/sld/sld_sysconfiles/periph_clk.sopcinfo' database could not be copied to ptile_4x4/qdb/_compiler/ghrd_agfb014r24b2e2v/root_partition/23.3.0/partitioned/1/sld_sysconfiles/periph_clk.sopcinfo. I would greatly appreciate your guidance and support in resolving this issue. Thanks & Regards Raju Satrasala Replies: Re: Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example Hi, For Linux bitstream error, please follow the below steps to run the pre-built binaries for Agilex® 7 FPGA F-Series PCIe Root Port Reference Design --> https://www.rocketboards.org/foswiki/Documentation/AgilexPcieRootPort.?elq_cid=11325872_ts1698719844198&erpm_id=12677771_ts1698719844198 1. Download the sd card image. https://www.rocketboards.org/foswiki/pub/Documentation/AgilexPcieRootPort/sdimage.tar.gz 2. Copy the images to Sd card using linux dd commands or windows-win32 Disk Imager utility. 3. Open the Sd card files in PC and replace the existing kernel.itb file with this https://www.rocketboards.org/foswiki/pub/Documentation/AgilexPcieRootPort/kernel.itb 4. Insert the SD card in board, change the switches as below- SW1: ON-OFF-OFF-ON SW2: all OFF SW3: OFF-OFF-ON-ON-ON-ON SW4: OFF-OFF-OFF-ON 5. Open the programmer, autodetect and select the AGILEX_HPS device in the JTAG scan chain. 6. Select the AGB014R24B device from the JTAG scan chain and click on Change File. 7. Program the .sof from https://www.rocketboards.org/foswiki/pub/Documentation/AgilexPcieRootPort/ROOTPORT_Release_1_0_ptile_4x4_hps.sof 8. Now you will see the bootloader starts but initially first time it will give the error and will stop at uboot. 9. Enter bootm at uboot. 10. Now the linux will start booting on board and enter with root login and password. 11. Enter the “lspci -v” to see the PCIe. Regards Tiwari Replies: Re: Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example Hi, As discussed on call, can you please use the same tool version 23.2 mentioned on below link for Design PCIe RootPort Quartus Compilation. https://www.rocketboards.org/foswiki/Documentation/AgilexPcieRootPort.?elq_cid=11325872_ts1698719844198&erpm_id=12677771_ts1698719844198 For linux bitstream errors, I will try at my end with pre-built binaries/images and will update you soon. Regards Tiwari Replies: Re: Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example Hi @Jeet14 , Thanks for your response. We are facing issue with Quartus Compilation of PCIe Rocket Board Example Design Project as well as Linux Boot Up. Thanks & Regards Raju Satrasala Replies: Re: Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example Hi Raju, Please help me to understand nature of the raised issue as I see two different issue on same forum thread. Are you facing issue which the Quartus/PD compilation issue or the linux boot up issue. Regards Tiwari Replies: Re: Compilation Error in Quartus Prime 23.3 for Agilex PCIe Root Port Design Example Hi Intel Embedded team, Appreciate if the team can help to look at this. Refer previous case at https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Agilex-Error-Sending-Bitstream/m-p/1535351#M26097 Customer issue on below during Linux boot-up Process, File checked, no corruption “Error sending bitstream!” “FPGA image is corrupted or invalid.” “SCRIPT FAILED: continuing…” " Unable to read file / " Regards, Wincent_Intel