Why does the Intel® Quartus® Prime Pro Edition software generate timing violations when using the Intel® Stratix® 10 L- and H-Tile Transceiver PHY IP in bonding mode? - Why does the Intel® Quartus® Prime Pro Edition software generate timing violations when using the Intel® Stratix® 10 L- and H-Tile Transceiver PHY IP in bonding mode? Description When using the Intel® Stratix® 10 L- and H-Tile Transceiver PHY IP in bonding mode, use the tx_coreclk from the master channel as the source clock for all of the other channels in the bonded interface. If this guideline is not met, you will see timing violations for a clock transfer from one tx_outclock domain to another. Resolution The information is scheduled to be updated in a future update of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide. Custom Fields values: ['novalue'] Troubleshooting FB: 1408300344; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']