Why doesn't my Hard IP for PCI Express HIP Reconfiguration block dynamically change the configuration register values? - Why doesn't my Hard IP for PCI Express HIP Reconfiguration block dynamically change the configuration register values? Description Due to a Quartus® II software limitation in the Hard IP Reconfiguration block, the ability to dynamically change read-only Configuration Space registers is failing. Resolution There are two possible workarounds for issue: 1) Use an LPM_CONSTANT Megafunction to generate your required input to the Hard IP, including the address (read and write) and writedata, for the required dynamic reconfiguration. Each address must be unique unless you are using the In-System Sources and Probe Editor. 2) Use sld_mod_ram_rom as shown in the design example linked below: hip-reconfig-workaround.qar Custom Fields values: ['novalue'] Troubleshooting NA False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']