How do I generate a downstream hot reset from the Altera Hard IP for PCI Express Avalon-ST Root Port? - How do I generate a downstream hot reset from the Altera Hard IP for PCI Express Avalon-ST Root Port? Description The PCI Express® Specification Revision 3.0 describes a Hot Reset and how it is signaled on the link. In the Altera® Root Port, setting bit[6] Secondary Bus Reset of the Bridge Control Register (0x03E), causes a Hot Reset. Refer to Section 7.5.3.6 of the PCIe Spec Revision 3.0. This is a Type 1 Configuration Space register, which is accessed by issuing a Type 0 Configuration TLP. Resolution Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']