Why is the waitrequest signal not asserted during reset when simulating the Low Latency 40-Gbps Ethernet Intel® Stratix® 10 IP Core? - Why is the waitrequest signal not asserted during reset when simulating the Low Latency 40-Gbps Ethernet Intel® Stratix® 10 IP Core? Description Due to a problem in the Intel® Quartus® Prime software release 17.1, in simulation, you will see the waitrequest signal stay de-asserted (low) even while reset is asserted. This violates the Avalon® Memory-Mapped Interface specification and may result in errors from some testbenches, but it is not a functional issue. Resolution To work around this problem, you can ignore this behavior, and either ignore the testbench errors or downgrade them to warnings. This problem is fixed beginning with version 18.0 of the Intel® Quartus® Prime Pro Edition Software Custom Fields values: ['novalue'] Troubleshooting FB: 492436; True ['Low Latency 40G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']