Why are there minimum pulse width violations in DDR5 Component External Memory Interfaces (EMIF) IP and DDR5 DIMM External Memory Interfaces (EMIF) IP of Agilex™ 7 FPGA M-Series and Agilex™ 5 FPGA D-Series devices? - Why are there minimum pulse width violations in DDR5 Component External Memory Interfaces (EMIF) IP and DDR5 DIMM External Memory Interfaces (EMIF) IP of Agilex™ 7 FPGA M-Series and Agilex™ 5 FPGA D-Series devices? Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, DDR5 Component External Memory Interfaces (EMIF) IP and DDR5 DIMM External Memory Interfaces (EMIF) IP might show minimum pulse width violations. Resolution It is safe to ignore these minimum pulse width violations. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15018915712 novalue ['Memory Controllers'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']