Error: SERDES receiver node 'ext_altlvds_rx:inst1|altlvds_rx:ALTLVDS_RX_component|ext_altlvds_rx_lvds_rx:auto_generated|rx_0' is not properly connected on the 'DPACLKIN' port - Error: SERDES receiver node 'ext_altlvds_rx:inst1|altlvds_rx:ALTLVDS_RX_component|ext_altlvds_rx_lvds_rx:auto_generated|rx_0' is not properly connected on the 'DPACLKIN' port Description You will see this error in the Intel® Quartus® II software version 11.0 when you enable DPA on the ALTLVDS_RX megafunction and use External PLL Mode in Intel® Stratix® V devices. To avoid this issue, perform the following steps: Change the following line of code in both the entity and component declaration in the top-level ALTVDS_RX design file: rx_dpaclock : IN STD_LOGIC_VECTOR (0 DOWNTO 0) to rx_dpaclock : IN STD_LOGIC; Resolution This problem is already fixed in the Intel® Quartus® II software version 11.0SP2. Related Articles How do I implement ALTLVDS in External PLL Mode for Stratix V, Arria V, and Cyclone V devices? Custom Fields values: ['novalue'] Troubleshooting 2205810117 False ['novalue'] ['novalue'] novalue novalue ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']