University Self-Guided Lab: Become an FPGA Designer in 4 Hours - 4 Hours This course gives you basic skills to design with Altera® FPGAs in 4 hour using a mixture of lecture, demonstrations & labs. Learn architectural features of Altera® FPGAs & how the Altera® Quartus® Prime software works. The labs train you to: Set up a design project Set assignments & compile a design Perform timing analysis Perform power analysis Download a design to hardware Debug with the Signal Tap logic analyzer The course is most beneficial using the Cyclone® V GX Starter Kit or the DE10-Lite Kit from Terasic. Consult Terasic/ Digikey websites for details on the kits. If you choose not to purchase a kit, you can complete all labs except Design Download & Debug. Links to download lab files are in the Notes section. Course Objectives At course completion, you will be able to: Describe the features that make up modern FPGA devices Use many of the common features of the Altera® Quartus Prime software including IP Generation, I/O assignments, compilation, timing analysis, power analysis, design Download and design debug Understand how to generate timing constraints for synchronous and asynchronous based systems Download a completed design from your PC to a development kit Use the signal Tap embedded logic Analyzer to debug your design Skills Required Basic understanding of digital logic design If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSWBECOME. FPGA_ODSWBECOME. <p>University Self-Guided Lab: Become an FPGA Designer in 4 Hours</p>