Getting Started with Software Design Flow for Altera® SoC FPGAs - 65 Minutes This training examines the software design flow required to implement software for an Altera® SoC FPGA with the Arm-based HPS as an FPGA Component IP. Through the description of the booting stages you will learn how to develop each software necessary for your system to boot all the way to the application. The course targets Agilex™ 5 SoC FPGA architecture and software flow and Golden System Reference Design. This course discusses the tools and methodology necessary to design and verify your system software as well. You will gain an understanding of exactly what’s required to implement your software with Altera® SoC FPGAs. Course Objectives At course completion, you will be able to: Explain the software development tools and flow for software development Understand the components and GSRD code Explain the Boot flow of the HPS as an FPGA Component IP Build the bootloaders and root file system for Altera® SoC FPGAs Select a compatible operating system to run on the Arm processor Perform FPGA-adaptive debug Skills Required Basic software development knowledge Preferably Hardware Integration knowledge using Quartus® Prime Software and Platform Designer If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OSOC2000. FPGA_OSOC2000. <p>Getting Started with Software Design Flow for Altera SoC FPGAs</p>