Why doesn't the Intel® Stratix® 10 Avalon-MM Interface PCIe* HIP reflect MSI-X parameters in the IP Catalog ? - Why doesn't the Intel® Stratix® 10 Avalon-MM Interface PCIe* HIP reflect MSI-X parameters in the IP Catalog ? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2 or earlier, the MSI-X parameters below shown in the GUI do not match the params in the generated RTL. - Table offset - Pending bit array (PBA) offset Resolution To work around this problem, modify the parameters below in the "altera_pcie_s10_hip_avmm_bridge.v". parameter [28:0] pf0_pci_msix_pba_offset = 29'h2000 , parameter [28:0] pf0_pci_msix_table_offset = 29'h3000 This problem is fixed in the Intel® Quartus® Prime Pro software version 19.3 and beyond. Custom Fields values: ['novalue'] Troubleshooting 1507323238 True ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.2 ['Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue'] - 2022-01-19