How should I place the QDR II/QDR II+ mem_cq and mem_cq_n pins in Arria® V GX/GT/ST/SX devices? - How should I place the QDR II/QDR II+ mem_cq and mem_cq_n pins in Arria® V GX/GT/ST/SX devices? Description From the device pinout file, there is only one pin location available for both mem_cq and mem_cq_n pins. Resolution For these Arria® V devices, complementary strobes are not supported so only one of the mem_cq or mem_cq_n pins will be used depending on the read latency setting. Custom Fields values: ['novalue'] Troubleshooting 1408189682 False ['QDR II and QDR II+ SRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']