Designing with Altera® Stratix® 10, Altera Arria® 10 & Altera Cyclone® 10 GX Hard IP for PCI Express* - 31 Minutes In this class, you will learn rules that must be followed to ensure proper placement of Altera® Stratix® 10, Altera® Arria® 10 and Altera® Cyclone® 10 GX FPGA Hard IP for PCI Express* blocks and transceiver channels, failure of which can lead to compilation errors and possibly board re-spins. You will learn how to select the best clock resource based on location along with PCI Express lane speed and configuration. You will learn how to set up and use Configuration via Protocol (CvP) using PCI Express to configure your target FPGA over the PCI Express link. You will also learn debugging tools and techniques to employ if issues arise when bringing up your PCIe link in a system. Course Objectives At course completion, you will be able to: Avoid board-level issues when choosing locations for Hard IP for PCI Express transceiver channels Selecting the right PLL for low-jitter transmit operation Enable CvP in your Altera® Stratix® 10, Altera® Arria® 10 and Altera® Cyclone 10 GX FPGA Describe the tools and techniques used to debug a Hard IP design Skills Required Some understanding of the PCI Express* Protocol specification is useful, but not required Familiarity with common high-speed transceiver architecture OR viewing the following Transceiver Basics course OR attending the Building Gigabit Interfaces in Altera® Arria® 10 Transceiver Devices Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus Prime Pro design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPCIDESIGNG10. FPGA_OPCIDESIGNG10. <p>Designing with Altera Stratix 10, Altera Arria 10 & Altera Cyclone 10 GX Hard IP for PCI Express*</p>