Why does the R-Tile IP for Compute Express Link* (CXL*) Type3 Design Example report the simulation error when selecting DK-DEV-AGI027RBES? - Why does the R-Tile IP for Compute Express Link* (CXL*) Type3 Design Example report the simulation error when selecting DK-DEV-AGI027RBES? Description Due to a problem in Quartus® Prime Pro Edition Software version 23.3 and earlier, you will observe a simulation error of R-Tile IP for Compute Express Link* (CXL*) Type3 Design Example when selecting DK-DEV-AGI027RBES (RevB B0 Dev kits). The error message will be similar to the one shown below: Error-[MPD] Module previously declared The module was previously declared at: "xxxx/intel_rtile_cxl_top_0_ed/hardware_test_design/common/mc_top/emif_ip/emif/altera_emif_arch_fm_191/sim/altera_emif_arch_fm_bufs.sv", 18 It is redeclared later at: "xxxx/intel_rtile_cxl_top_0_ed/hardware_test_design/common/mc_top/emif2_ip/emif2/altera_emif_arch_fm_191/sim/altera_emif_arch_fm_bufs.sv", 18: token is 'altera_emif_arch_fm_bufs' module altera_emif_arch_fm_bufs #( Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. To work around this problem, refer to the following modification of the file list: 1. Open /sim_filelist "ed_ip_filelist.f". 2. Comment out all lines related to “emif2” and run the simulation . Custom Fields values: ['novalue'] Troubleshooting 15014743871 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']