When using Intel® Stratix® 10 how do I recover from an error state after sending a corrupted partial reconfiguration bitstream? - When using Intel® Stratix® 10 how do I recover from an error state after sending a corrupted partial reconfiguration bitstream? Description When the Intel® Stratix® 10 Partial Reconfiguration Controller Intel® FPGA IP detects a corrupted partial bitstream, it sets status[2..0] = 3'b100 = PR_ERROR is triggered . The avst_sink_ready signal is de-asserted and the Partial Reconfiguration Controller Intel® FPGA IP will not accept any further partial reconfiguration bitstream until the IP is reset using the reset port. Before resetting the Partial Reconfiguration Controller Intel® FPGA IP it is necessary to ensure that the remaining partial bitstream is flushed from the Avalon® streaming pipeline, and only then assert the reset to the Partial Reconfiguration Controller Intel® FPGA IP. Resolution To work around this problem implement RTL to monitor the status[2..0] port and generate a dummy avst_sink_ready signal to the Intel® Stratix® 10 Partial Reconfiguration Controller Intel® FPGA IP Master when PR_ERROR is indicated and ensure avst_sink_valid has finished toggling. This will ensure the remaining partial reconfiguration bitstream is flushed from the Avalon® streaming pipeline, then apply the reset to the Intel® Stratix® 10 Partial Reconfiguration Controller Intel® FPGA IP. Once completed it will be possible to start sending a new good partial reconfiguration bitstream to the Partial Reconfiguration Controller Intel® FPGA IP. Custom Fields values: ['novalue'] Troubleshooting 16011850084 False ['Partial Reconfiguration Controller Arria® 10 Cyclone® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 20.3 ['Stratix® 10 DX FPGA', 'Stratix® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']