Why do I see Siemens QuestaSim* and Cadence Xcelium* simulation failure for the F-Tile 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example? - Why do I see Siemens QuestaSim* and Cadence Xcelium* simulation failure for the F-Tile 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example? Description Due to an issue with the Quartus® Prime Pro Edition software version 25.3.1, you may see ModelSim*– FPGA Edition and Xcelium* simulation failures for F-Tile 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Examples. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 15017367283 novalue ['Interfaces Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex™ 7 FPGAs and SoCs'] ['Simulation Dev Tools ModelSim'] ['novalue'] ['novalue']