Quartus Compilation Fails For SerialLite III IP Core Simplex Source Design with ECC Enabled - Quartus Compilation Fails For SerialLite III IP Core Simplex Source Design with ECC Enabled Description The Quartus compilation reports an error in the fitter for SerialLite III IP core simplex source design configured with ECC enabled. You will encounter the following error message: Error: Argument <clk_object> is an object filter that matches no objects. Specify one matches only one object. while executing "get_clock_info -period *seriallite_iii_a10_0|source_clock_gen*user_clock_inst|altera_iopll_inst|outclk0" invoked from within "if { [get_collection_size [get_registers -nowarn *source_adaptation_ecc|dcfifo_s5m20k:dcfifo_inst*dcfifo_ecc|raddr_g_completed*]] > 0 } { set_min_d..." (file "sl3_source_ac/seriallite_iii_a10_160/synth/seriallite_iii_streaming.sdc" line 73) This is due to the following seriallite_iii_streaming.sdc constraints that can only be applied for a duplex design. if { [get_collection_size [get_clocks -nowarn user_clock_tx]] eq 0 } { set wclk_period [get_clock_info -period *seriallite_iii_a10_0|source_clock_gen*user_clock_inst|altera_iopll_inst|outclk0] } if { [get_collection_size [get_clocks -nowarn *seriallite_iii_a10_0|source_clock_gen*user_clock_inst|altera_iopll_inst|outclk0]] eq 0 } { set wclk_period [get_clock_info -period user_clock_tx] } Resolution Change "user_clock_tx" to "user_clock". Replace the existing constraints to the following example: if { [get_collection_size [get_clocks -nowarn user_clock_tx]] eq 1 } { set wclk_period [get_clock_info -period user_clock_tx] } if { [get_collection_size [get_clocks -nowarn *seriallite_iii_a10_0|source_clock_gen*user_clock_inst|altera_iopll_inst|outclk0]] eq 1 } { set wclk_period [get_clock_info -period *seriallite_iii_a10_0|source_clock_gen*user_clock_inst|altera_iopll_inst|outclk0] } if { [get_collection_size [get_clocks -nowarn user_clock]] eq 1 } { set wclk_period [get_clock_info -period user_clock] } This issue will be fixed in a future release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']