Why does the mem_reset_n signal toggle multiple times at the first assertion in the Skip Calibration simulation mode? - Why does the mem_reset_n signal toggle multiple times at the first assertion in the Skip Calibration simulation mode?
Description This observation is expected and does not cause any malfunction of the PHY operation during simulation. In Full Calibration simulation mode, the EMIF IP performs a full reset initialization sequence, and consequently, those glitches don't occur.
Custom Fields values:
['novalue']
Troubleshooting
FB: 453709;
False
['External Memory Interfaces Arria® 10 FPGA IP']
['novalue']
novalue
novalue
['Arria® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
external_document