Cyclone® 10 GX FPGA Overview - Cyclone 10 GX FPGA is optimized for high-bandwidth performance applications such as machine vision. Product Pages Broadcast Industrial Medical Overview The Cyclone 10 GX FPGA is built on a high-performance 20 nm process, offering a performance advantage for cost-sensitive applications. Cyclone 10 GX FPGA Product Table Benefits Built on 20 nm process technology and programmable with the advanced Quartus design environment, achieve twice the performance of previous-generation Cyclone V FPGAs along with 12.5 Gbps chip-to-chip transceiver I/O and 6.6 Gbps backplane support. Enhanced Core Architecture with High-Bandwidth Integrated Transceivers The Adaptive Logic Module architecture – same as previous-generation FPGAs – allows the efficient implementation of logic functions, simplified conversion of intellectual property (IP) cores between the device generations, and improved timing closure in devices. Improved Efficiency and Timing Closure Cyclone 10 GX FPGAs offer a comprehensive set of advanced power-saving features with power-optimized MultiTrack routing and core architecture reducing power consumption. Advanced Power Saving Key Features 12.5 Gbps chip-to-chip transceiver support, 6.6 Gbps backplane support along with hard PCI Express (PCIe) IP supporting PCIe 2.0. Transceivers High-performance external memory interface with up to 1,866 Mbps DDR3. External Memory Interface Each I/O bank contains GPIOs featuring 1.434 Gbps LVDS I/Os and support a wide range of I/O interfaces. General Purpose I/O IEEE 754-compliant hard floating-point digital signal processing (DSP) blocks. Digital Signal Processing Applications Real-time control, vision processing, and automation Industrial Imaging, diagnostics, and portable medical devices Medical Video capture, processing, and transport Broadcast and Pro AV Dev Kits, IP, Example Designs & Software Get Started: Development Kits, IP, Example Designs and Software Dev Kit Cyclone 10 GX FPGA Development Kit High-speed transceiver and PCIe 2.0 evaluation platform. IP Multi-Rate Ethernet PHY FPGA IP The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration. HDMI IP Core The High-Definition Multimedia Interface (HDMI) IP provides support for next-generation video display interface technology. Example Designs FPGA Developer Site GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral. Example Design Store This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production. Software Quartus® Prime Pro Edition Design Software Documentation Documents Documentation Cyclone 10 GX FPGA Device Overview Cyclone 10 GX FPGA Product Table Cyclone 10 GX FPGA Device Data Sheet Support Resources Cyclone® 10 GX FPGA