Why do I get incorrect read data from my Simple Dual Port RAM when the clock enable 1 signal is inverted? - Why do I get incorrect read data from my Simple Dual Port RAM when the clock enable 1 signal is inverted? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.3 and later, Intel Agilex® 7 FPGA M20K simple dual-port RAM read data may be incorrect when configured as follows: Port: The clocken1 is inverted Parameters: altera_syncram_component.intended_device_family = "Agilex" altera_syncram_component.operation_mode = " DUAL_PORT" altera_syncram_component.ram_block_type = "M20K" altera_syncram_component.clock_enable_input_b = "BYPASS" altera_syncram_component.clock_enable_output_b = "NORMAL" altera_syncram_component.address_reg_b = "CLOCK1" altera_syncram_component.outdata_reg_b = "CLOCK1" Resolution To work around this problem, download and install the appropriate patch. Download and install the following Patch 0.31 for the Intel® Quartus® Prime Pro Edition Software v20.4: Intel Quartus Prime Pro Edition Software v20.4 Solution Patch 0.31 for Windows (.exe) Intel Quartus Prime Pro Edition Software v20.4 Solution Patch 0.31 for Linux (.run) Readme for Intel Quartus Prime Pro Edition Software v20.4 Solution Patch 0.31 (.txt) Download and install the following Patch 0.02 for the Intel Quartus Prime Pro Edition Software v21.1: Intel® Quartus® Prime Pro Edition Software v21.1 Solution Patch 0.02 for Windows (.exe) Intel® Quartus® Prime Pro Edition Software v21.1 Solution Patch 0.02 for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software v21.1 Solution Patch 0.02 (.txt) This problem is fixed starting with the Intel Quartus Prime Pro Edition Software v21.2. Custom Fields values: ['novalue'] Troubleshooting 1508988935 1508932295 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 19.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']