Simulation Error QDR II and QDR II SRAM Controller with UniPHY - Simulation Error QDR II and QDR II SRAM Controller with UniPHY Description Inconsistency between module definition and instantiation may cause some simulators to produce an error message. Resolution The workaround for this issue is to manually edit the oct_control.v and clock_pair_generator_config.v files, and remove specific port names from each, as described below. Port Names to Remove from clock_pair_generator_config.v File: <variation_name>/rtl/<variation_name>_clock_pair_generator_config.v Module: arriaii_pseudo_diff_out Instance: pseudo_diffa_0 Port names to remove: .dtc� .dtcbar� .oebout� .oeout� .dtcin� .oein Port Names to Remove from oct_control.v File: <variation_name>/rtl/<variation_name>_oct_control.v Module: arriaii_termination_logic Instance: sd2a_0 Port names to remove: .scanout� .s2pload� .scanclk� .scanenable� .scanin� .serdata Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 10.0.1 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']