RapidIO IP Core Arria V GZ Variations Generate an Incorrect SDC File in Qsys - RapidIO IP Core Arria V GZ Variations Generate an Incorrect SDC File in Qsys
Description If you generate a RapidIO IP core instance in Qsys, and specify target device family Arria V GZ, your RapidIO IP core generates an incorrect SDC file. The file specifies a clock connection to an invalid clock.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
14.1
12.1
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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