Why is data corrupted when performing loopback using the Arria 10 Hard IP for PCI Express in Gen1 and Gen2 modes? - Why is data corrupted when performing loopback using the Arria 10 Hard IP for PCI Express in Gen1 and Gen2 modes? Description The Arria® 10 Hard IP for PCI Express® performing loopback in Gen1 and Gen2 modes transmits corrupted data because of an incorrect Quartus® Prime bit setting. Resolution For Quartus Prime 15.1.2, install the appropriate patch. Regenerate your PCIe® Hard IP core and recompile the design. For Arria 10 GX/GT/SX 1150ES3 or production silicon use patch 2.01. For Arria 10 GX/GT/SX 660ES2 or production silicon use patch 2.05. For Arria 10 GX/GT/SX 1150ES, 1150ES2, 660ES silicon use patch 2.14. This issue is fixed in Quartus Prime software 16.0 and later. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.0 novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']