GTS PCIe Hard IP - GTS PCIe Hard IP is a full featured protocol stack with AXI4-Stream user interface available on Agilex™ 5 and Agilex™ 3 FPGAs. Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 4.0 x4 (E-Series) and PCIe 4.0 x8 (D-Series) configurations for Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes. Agilex™ 3 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 3.0 x4 configurations for Root Port and Endpoint modes. PCI Express (IP) Aerospace ASIC Proto Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Wireless GTS PCIe Hard IP Key Features Complete PCIe Protocol Stack in Hard IP – Full implementation of Transaction, Data Link, and Physical Layers. Offering Brief Yes No No Yes Encrypted Verilog Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Yes Yes Offering Brief Production a1JUi000004N4rpMAC What's Included Encrypted Verilog Source Code Ordering Information No license required Direct a1JUi000004N4rpMAC Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-10-24T17:23:01.000+0000 GTS PCIe Hard IP is a full featured protocol stack with AXI4-Stream user interface available on Agilex™ 5 and Agilex™ 3 FPGAs. Altera Solutions