Why does the external memory interface calibration hang after a CvP update when using the DDR3, DDR2 or LPDDR2 UniPHY hard memory controller? - Why does the external memory interface calibration hang after a CvP update when using the DDR3, DDR2 or LPDDR2 UniPHY hard memory controller? Description Due to a problem in the Quartus® II software, when configuring a SOF file through the Configuration via Protocol (CvP) method with a design that includes the UniPHY hard memory controller, you may observe that calibration fails after the CvP update occurs. The external memory interface calibration status signals local_cal_fail and local_cal_success never become asserted. This issue occurs because the content of the M20K/M10K RAM memory used for the calibration process was corrupted after the CvP update. Resolution Contact Intel® for details of the workaround. Custom Fields values: ['novalue'] Troubleshooting 1408041666 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']