Error Message When Recompiling a Project - Error Message When Recompiling a Project Description If you move the directory containing your Quartus II project, or rename your Quartus II project and recompile it without regenerating the DDR or DDR2 SDRAM Controller, you may receive the following error: Error: DDR timing cannot be verified until project has been successfully compiled. This error indicates that some of the settings files contain references to the previous location or project name and the verify timing script is unable to find the current project. This issue affects all configurations. The timing script does not verify your design. Resolution Regenerate your controller in IP Toolbench and recompile the project. The timing analysis script now completes correctly. This issue will not be fixed. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']