Initial Design Review for Arria® 10 SoC FPGA Designs - 28 Minutes In this training, you will learn a general process for conducting an initial design review for any FPGA design. Then, we will explore the areas for review for an Arria® 10 SoC FPGA design: HPS Design, Board Design, and Embedded Software Design. The course will follow the checklists and advice offered in the Arria® 10 SoC Device Design Guidelines document. Each discussion of a subject area for review will include 3 sections: reference documents, design considerations, and deliverables and actions. Course Objectives At course completion, you will be able to: Describe a general process for conducting an initial design review Describe the Arria® 10 SoC FPGA design considerations that should be reviewed Name the deliverables that should be expected from each team member Skills Required Familiarity with the Basic architecture of a SoC FPGA If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OIDR100. FPGA_OIDR100. <p>Initial Design Review for Arria 10 SoC FPGA Designs</p>