PCI Express Design Example Does Not Always Close Timing in Stratix V GX and HardCopy IV GX Devices in 250 MHz Mode - PCI Express Design Example Does Not Always Close Timing in Stratix V GX and HardCopy IV GX Devices in 250 MHz Mode
Description The PCI Express design example discussed in both the “ Getting Started ” and “ Testbench and Design Example ” chapters of the PCI Express Compiler User Guide does not always close timing in Stratix V GX and HardCopy IV GX devices running at 250 MHz in the Quartus II 10.0 release. Resolution This issue has no workaround. This issue is fixed in version 10.0 SP1 of the PCI Express Compiler.
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
10.0.1
10.0
['Stratix® V FPGAs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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