Why does the Intel® Stratix® 10 HBM2 IP calibration success signal stay low at Tj less than 0°C ? - Why does the Intel® Stratix® 10 HBM2 IP calibration success signal stay low at Tj less than 0°C ? Description The minimum operating temperature for HBM2 DRAM is 0°C. When the Intel® Stratix® 10 MX FPGAs must be configured at less than 0°C, the HBM2 controller will read the junction temperature (Tj) using the TSD (temperature sense diode) and will hold the controller in reset. The local_cal_success signal and AXI_*_ready signals won't be asserted until Tj reaches 0°C or greater. Custom Fields values: ['novalue'] Troubleshooting 1507296133 False ['High Bandwidth Memory (HBM2) Interface IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.1 ['Stratix® 10 MX FPGA'] ['novalue'] ['novalue'] ['novalue']