Nios® V Processors Booting - Same course in Japanese: Nios® V プロセッサーのブート 20 Minutes This Online training provides an overview of the Nios® V processors’ booting and configuration methods. As Altera®'s next generation soft core processor based on the open-source RISC-V, Nios V processors offer different booting methods targeting each family and device with support in any version of Quartus® Prime Software. This walk-through covers types of memories, methods, and a summary of configurations in Platform Designer and BSP editor to configure your method. Course Objectives At course completion, you will be able to: Understand the different booting methods depending on the Altera® FPGA family being targeted Review the steps to implement the configuration in the BSP editor and Platform Designer custom instructions in Platform Designer inside Quartus Prime Software for execute in place and to use a boot copier to RAM Skills Required Introductory level of Quartus Prime Software and Platform Designer Basic knowledge of booting flow Basic programming skills If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com Reference Course Code: FPGA_ONVBOOT. FPGA_ONVBOOT. <p>Nios V Processors Booting</p>