Non-leveled DDR2 Topology Fails Timing with Stratix V Devices for DDR2 and DDR3 SDRAM Controller with UniPHY - Non-leveled DDR2 Topology Fails Timing with Stratix V Devices for DDR2 and DDR3 SDRAM Controller with UniPHY
Description A non-leveled topology does not work with the DDR2 protocol targeting Stratix V. devices. Resolution There is no workaround for this issue.
Custom Fields values:
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Troubleshooting
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True
['novalue']
['FPGA Dev Tools Quartus II Software']
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11.0.1
['Stratix® V FPGAs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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