Why is the "pfl_flash_access_request" signal in the Parallel Flash Loader (PFL) megafunction not being deasserted when I try to configure a Stratix V ES device via a Fast Passive Parallel (FPP) configuration scheme? - Why is the "pfl_flash_access_request" signal in the Parallel Flash Loader (PFL) megafunction not being deasserted when I try to configure a Stratix V ES device via a Fast Passive Parallel (FPP) configuration scheme? Description If you are configuring a Stratix® V ES device with the PFL via a FPP configuration scheme using the Quartus® II software versions 12.0 SP1 or 12.0 SP2, you will see that the "pfl_flash_access_request" signal in the PFL megafunction will be asserted when it starts to access the flash device, but will never de-assert after the FPGA configuration is completed. Resolution This is fixed in the Quartus II software version 12.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0.1 ['MAX® V CPLDs', 'Stratix® V FPGAs', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']