Are there any known issues with the Stratix V Low Latency PHY when using an embedded reset controller in Quartus II software version 12.0? - Are there any known issues with the Stratix V Low Latency PHY when using an embedded reset controller in Quartus II software version 12.0? Description Yes, there is a known bug in the Stratix® V Low Latency PHY when using an embedded reset controller in Quartus® II software version 12.0. When configured for a bonded interface, each channel has its own reset. When configured for a non-bonded interface, all channels share a reset. The correct behaviour should be When configured for a bonded interface, all channels share a reset. When configured for a non-bonded interface, each channel has its own reset. Resolution To work around this problem, upgrade to Quartus II Software Version 12.0SP1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0.1 12.0 ['Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']