Why does the IOPLL in Arria 10 devices fail to lock and generate no output clock when the I/O standard of the reference clock input pin is set to Differential HSTL or Differential SSTL? - Why does the IOPLL in Arria 10 devices fail to lock and generate no output clock when the I/O standard of the reference clock input pin is set to Differential HSTL or Differential SSTL? Description You may observe that the IOPLL in Arria® 10 devices fails to lock and generate no output clock when the I/O standard of the reference clock input pin is set to Differential HSTL or Differential SSTL in the Quartus® Prime software. This is because Arria 10 devices only support the following I/O standards for the IOPLL reference clock input : - Single-ended I/O standards - LVDS Resolution If Differential HSTL or Differential SSTL signalling is used to drive the reference clock input pin on your board, assign a true differential I/O standard (e.g. LVDS) to this pin in the Quartus Prime software to support the Differential HSTL and Differential SSTL electrical specifications. The Quartus Prime software version 16.0 includes a legality check to prevent users from setting pseudo-differential I/O standards to the reference clock input pin. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']