Why are there error/warning messages in the FASTSIM mode when simulated with Synopsys verification IP? - Why are there error/warning messages in the FASTSIM mode when simulated with Synopsys verification IP? Description In the FASTSIM mode, a simplified PMA abstract model is used to improve the overall simulation time for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express. The following error and warning messages are expected in the FASTSIM mode when simulated with Synopsys verification IP. It is due to PHY calibration being bypassed in the simulation. It is safe to ignore the error and warning messages. UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 382510.547 ns: uvm_test_top.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_14] : New min half bit period seen (was 0.062500, now is 0.048750 ns) - SERDES unlocked. UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 519982.547 ns: uvm_test_top.secondary_tests_1.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_1] : New min half bit period seen (was 0.062500, now is 0.048750 ns) - SERDES unlocked. UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 508334.547 ns: uvm_test_top.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_4] : New min half bit period seen (was 0.062500, now is 0.048750 ns) - SERDES unlocked. UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 389018.547 ns: uvm_test_top.secondary_tests_3.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_3] : New min half bit period seen (was 0.062500, now is 0.048750 ns) - SERDES unlocked. UVM_ERROR /p/psg/EIP/synopsys/vip/vg_P-2019.06F/vip/svt/pcie_test_suite_svt/P-2019.06-1/design_dir/src/sverilog/vcs/pciesvc_serdes.sv(242) @ 510328.547 ns: uvm_test_top.env.pcie_env.rc_env.rc_agent.port0.pl0 [register_fail:ACTIVE_PL_LANE_SERDES:PROTOCOL:serdes_new_min_seen_3] : New min half bit period seen (was 0.062500, now is 0.048750 ns) - SERDES unlocked. Resolution There is no plan to fix the error and warning messages. Custom Fields values: ['novalue'] Troubleshooting 16018038847 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 22.3 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']