Why do I see a disparity error in my JESD204B receiver device when using the JESD204B Intel® FPGA IP in TX mode in Intel® Stratix® 10 devices with E-Tile transceivers? - Why do I see a disparity error in my JESD204B receiver device when using the JESD204B Intel® FPGA IP in TX mode in Intel® Stratix® 10 devices with E-Tile transceivers? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1, when using the JESD204B Intel® FPGA IP in TX mode in Intel® Stratix® 10 devices with E-Tile transceivers, the intellectual property (IP) will introduce a disparity error when configured for a single lane ( L=1) in bonded mode. Resolution To work around this problem, when configuring the JESD204B Intel® FPGA IP IP in L=1 mode, enable the non-bonded mode. This problem is fixed strating from Intel® Quartus® Prime Pro Edition Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1507180758, 1507182300 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.1 ['Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-10