Why is the timestamp value of the Stratix® 10 FPGA Hard IP for PCI Express* IP Link Inspector overestimated? - Why is the timestamp value of the Stratix® 10 FPGA Hard IP for PCI Express* IP Link Inspector overestimated? Description Due to a problem in the Stratix® 10 FPGA Hard IP for PCI Express* Link Inspector, you may observe that the timestamp value is larger than the actual time. For example, when using the Stratix® 10 FPGA Hard IP for PCI Express* coreclkout at 125MHz, the timestamp value will show approximately 20% over the estimated value (12ms compared to the actual 10ms). This is due to a discrepancy between the user-defined coreclkout at 125MHz or 250MHz, and the 100MHz clock always used by Link Inspector. Resolution To work around this problem, apply a multiplication factor on the timestamp value as shown below. When using a 125MHz coreclkout , multiply the timestamp value by a multiplication factor of 0.8 (100MHz / 125MHz). When using a 250MHz coreclkout , multiply the timestamp value by a multiplication factor of 0.4 (100MHz / 250MHz). This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting FB587439 True ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']