High-Level Synthesis (HLS) for FPGA Acceleration - This course provides comprehensive training in the Altera HLS Compiler Pro Edition. FPGA Authority is an Altera® certified trainer that provides in-depth, technically detailed instruction covering the complete FPGA and SoC design process. Training spans RTL hardware design, embedded… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA High-Level Synthesis (HLS) is a transformative methodology that enables hardware designers and software engineers to describe complex algorithms in C++ and automatically compile them into synthesizable RTL code, dramatically accelerating FPGA development cycles for compute-intensive applications. This course provides comprehensive training in the Altera HLS Compiler Pro Edition and its integration with the Altera Quartus Prime design environment. Students learn HLS-specific C++ language extensions, optimization directives, memory architecture strategies, and the complete design flow from algorithmic specification to a programmed FPGA target. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless High-Level Synthesis (HLS) for FPGA Acceleration Key Features Offering Brief No No No No Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA 2 Days No No English Offering Brief Production Windows,Linux a1JUi0000096ZxBMAU - Solid proficiency in C or C++ programming with a fundamental understanding of digital logic design Hardware and Software Engineers, FPGA Designers, SoC Developers, Verification Engineers, System Architects, Managers What's Included PDF of slides, lab manual and lab files where required Ordering Information High-Level Synthesis (HLS) for FPGA Acceleration a1JUi0000096ZxBMAU Production EDA Tools / IDE Education / Training a1MUi00000GbNhBMAV a1MUi00000GbNhBMAV Member 2026-06-08T23:50:02.000+0000 This course provides comprehensive training in the Altera HLS Compiler Pro Edition. Partner Solutions