Why does the interface 1 port simulate incorrectly when the abstract phy simulation model is used in the Intel® Arria® 10 DDR4 Ping Pong PHY IP? - Why does the interface 1 port simulate incorrectly when the abstract phy simulation model is used in the Intel® Arria® 10 DDR4 Ping Pong PHY IP? Description When using the Intel® Quartus® Prime software version 17.1.2 or earlier, you may see the interface 1 port simulate incorrectly when the Intel Arria® 10 DDR4 Ping Pong PHY IP is configured with both the Abstract phy for simulation option and the Write DBI option enabled. Note that the interface 0 port simulates correctly. Resolution This problem is fixed in the Intel® Quartus® Prime software version 18.0 or newer. Custom Fields values: ['novalue'] Troubleshooting FB: 2205660782; True ['External Memory Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 novalue ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']